1. Field of the Invention
This invention relates to a semiconductor device and a manufacturing method thereof.
2. Description of the Related Art
Conventional semiconductor devices include one called a chip size package (CSP). The CSP literally means a semiconductor package having substantially the same plane size as that of a semiconductor chip. Recently, a semiconductor chip has emerged in which external connection electrodes can not be disposed within about the same plane size as that of the semiconductor chip, along with an increase in the number of external connection electrodes. For such a semiconductor chip, a structure is employed in which the external connection electrodes are disposed within a plane size that is one size larger than that of the semiconductor chip. Jpn. Pat. Appln. KOKAI Publication No. 2004-221417 describes semiconductor device having such a structure. In this patent, in order to provide solder balls as connection terminals outside a size of a semiconductor construct, there is provided a device having following structures the semiconductor construct having a plurality of columnar electrodes on an upper surface side is bonded to an upper surface of a base plate via a bonding layer. An insulating layer is provided on the upper surface of the base plate around the semiconductor construct. An upper layer insulating film is provided on upper surfaces of the semiconductor construct and the insulating layer. Openings are provided in the upper layer insulating film on the columnar electrodes of the semiconductor construct. Upper layer wiring line are provided on an upper surface of the upper layer insulating film in such a manner as to connect the respective upper layer wiring lines to the columnar electrodes of the semiconductor construct via the openings of the upper layer insulating film a part except for a connection pad portion of each of the upper layer wiring lines is covered with an overcoat film. The solder ball is provided on the connection pad portion of each the upper layer wiring line.
In the meantime, in the conventional semiconductor device described above, the upper layer wiring line is formed by electrolytic plating, but a part of the upper layer wiring line is formed in the opening of the upper layer insulating film so that it is connected to the columnar electrode of the semiconductor construct via the opening of the upper layer insulating film. On the other hand, if a diameter of the columnar electrode is reduced due to higher density of the semiconductor construct called the CSP, a diameter of the opening formed in the upper layer insulating film on the columnar electrode is also reduced accordingly. Further, if air bubbles or the like enter the opening of the upper layer insulating film having a small diameter when the electrolytic plating is performed to form the upper layer wiring line, the air bubbles or the like that entered are not easily discharged, so that there is a problem that a plating solution does not infiltrate into the opening containing the air bubbles or the like, that voids are produced, and that breaking of the wiring lines and a loose connection are caused.